Field of the Invention
This invention relates in general to a method of fabricating a dynamic random access (DRAM) memory device, and more particularly to a method of fabricating a DRAM with precise contact opening.
Referring to FIG. 1, on a p-type substrate 10, at least one field region is defined so that the active region for forming devices is isolated by field oxide 11. Then, a gate oxide layer, a polysilicon layer and a cap oxide layer are successively formed on the substrate 10. Theses layers are then defined to a gate electrode structure including: a gate oxide layer 12, a polysilicon layer 13 and a cap oxide layer 14 shown in FIG. 1. Next, a oxide spacer structure 15 is formed at the periphery of the gate electrode structure. The self-aligned process is then performed to form source/drain regions 16a, 16b on the substrate 10 and therefore a MOS transistor is completed.
Next, as shown in FIG. 1B, a blanket insulating layer 17, such as an oxide layer, is formed on the substrate 10 and the gate electrode structure. A photoresist layer 18 is formed over the insulating layer 17. The insulating layer 17 is then patterned by exposure, development and the related processes to form a self-aligned contact 19, exposing one of the source/drain regions, for example, source/drain region 16a, as in FIG. 1C. Finally, a conductive layer 20 is formed to fill the contact opening 19 and then patterned to form a lower electrode. The conductive layer 20 can be a doped polysilicon layer.
In the above-mentioned conventional process, the insulating material in the contact opening has to be completely removed by the self-align etching process so that over-etching step is usually utilized to ensure the formation of the contact window. However, the cap oxide 14a is usually partially etched and a portion of the insulating material 17a is usually left on the oxide spacer 15 in the contact window 19, covering partially the surface of the source/drain regions 16a. As a result, the electrically coupling contact area of the conductive layer and source/drain region shrinks. Under the requirement of high integrated circuit (IC) integrity, the size of each device has to be decreased. However, the formation of the residue insulating layer 17a along the oxide spacer makes the formation of the contact window even more difficult and size-shrinking of self-align contact window results in high contact resistance. Consequently, the difficulties in processing results in low yield of high density DRAM. Over-etching of the cap oxide makes insufficient isolation effect between the gate electrode and the conductive layer and therefore reduce the reliability.